Pulse-based flip-flop

ABSTRACT

A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal. The pulse-based flip-flop comprises a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal and a pulse generator including a NAND gate, a variable delay, and a first inverter, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal. The NAND gate receives the clock signal and an output signal of the variable delay and outputs the second clock pulse signal. The first inverter receives the first clock pulse signal and outputs the second clock pulse signal. The variable delay receives the clock signal and the second clock pulse, and an output signal of the variable delay feeds back to the NAND gate.

PRIORITY STATEMENT

This application claims priority of Korean Patent Application Nos.2003-84965, filed on Nov. 27, 2003 and 2004-18004, filed on Mar. 17,2004, in the Korean Intellectual Property Office, the disclosure ofwhich is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the lnvention

The present invention relates to a pulse-based flip-flop.

2. Description of the Related Art

Flip-flops and latches may be used as data storage devices in integratedsemiconductor circuits. A flip-flop may sample an input signal andconvert the input signal into an output signal based upon an clocksignal. A latch may differ from a flip-flop in its signal processing inthat the latch may continuously sample an input signal and may convertthe input signal into an output signal based on clock pulses that it mayreceive.

FIG. 1 illustrates a block diagram of a conventional pulse-basedflip-flop. The pulse-based flip-flop 100 may include of a latch 110 forconverting input data DIN into output data DOUT in response to a firstclock pulse signal and a second clock pulse signal ˜φ and φ generated bya pulse generator 120. The pulse-based flip-flop 100 may have an idealoperating speed and power consumption characteristics because thepulse-based flip flop may use a single latch 110 unlike a master-slaveflip-flop, which may be constructed with two latches, a master latch anda slave latch, each. of which may be composed of at least four gates.Referring to FIG.2, the pulse generator 120 of the pulse-based flip-flop100 may include three serially connected inverters, 122,124, and 126.The first inverter 122, which may receive a clock signal CLOCK, an NANDgate 128, which may receive the clock signal CLOCK and an output signalof the third inverter 126, and may output a first clock pulse signal ˜φ.A fourth inverter 130, which may receive the output of the NAND gate128, may output a second clock pulse signal φ. The delay time of thefirst, second, and third inverters, 122, 124 and 126, may determine thepulse widths of the first and second clock pulse signals ˜φ and φ.

However, the pulse generator 120 may have a large chip area and/or ahigher power consumption than conventional latches which may be used inflip-flops because the pulse generator may be composed of more than fourgates. The high power consumption and/or large chip area may not beideal when a pulse-based flip-flop is used in a circuit with high-speedoperation and/or low power consumption.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention provide a pulse-basedflip-flop that may include a pulse generator and/or a latch composed ofa smaller number of gates than conventional pulse generators. Exemplaryembodiments provide a pulse-based flip-flop with reduced powerconsumption and/or chip area in comparison with conventional pulse-basedflip flops.

An exemplary embodiment of the pulse-based flip-flop may include a latchfor latching a data input signal in response a first clock pulse signaland a second clock pulse and a pulse generator for receiving a clocksignal for generating the first clock pulse signal and the second clockpulse signal.

According to an embodiment of the present invention, a pulse generatorincludes a NAND gate for receiving a clock signal and an output of avariable delay circuit, and outputs a first clock pulse signal; a firstinverter for receiving the output of the NAND gate and outputs thesecond clock pulse signal; the variable delay circuit for receiving theclock signal and the output of the first inverter and feeds an outputsignal back to the NAND gate; a second inverter for receiving the outputof the variable delay; and an NMOS transistor that may be connectedbetween the output of the variable delay and a ground voltage, and gatedto an output of the second inverter.

According to another embodiment of the present invention, a pulsegenerator comprising a NAND gate for receiving a clock signal and anoutput of a variable delay circuit, and outputting a first clock pulsesignal, a first inverter for receiving an output of the NAND gate andoutputs a second clock pulse signal; the variable delay circuit forreceiving the clock signal and the output of the first inverter, andfeeds an output signal back to the NAND gate; a second inverter forreceiving the output of the variable delay; a first NMOS transistorhaving a drain connected to the output of the variable delay circuit anda gate for receiving a clock signal; and a second NMOS transistor havinga drain connected to the source of the first NMOS transistor, a gateconnected to an output of the second inverter and a source connected toa ground voltage.

According to another embodiment of the present invention, a pulsegenerator comprising a NAND gate for receiving a clock signal, an enablesignal and a output of a variable delay circuit, and outputting a firstclock pulse signal; a first inverter for receiving the output of theNAND gate and outputs a second clock pulse signal; the variable delaycircuit for receiving the clock signal and the output of the firstinverter, and feeds an output signal back to the NAND gate; a secondinverter for receiving the output of the variable delay circuit; and anNMOS transistor having a source connected to the output of the variabledelay circuit, a drain connected to aground voltage and a gate connectedto an output of the second inverter.

According to another embodiment of the present invention, a pulsegenerator comprising a NAND gate for receiving a clock signal, an enablesignal and an output of a variable delay circuit, and outputting a firstclock pulse signal; a first inverter for receiving the output of theNAND gate and outputting a second clock pulse signal; the variable delaycircuit for receiving the clock signal and an output of the firstinverter, and feeds the output signal back to the NAND gate; a secondinverter for receiving the output of the variable delay circuit; a firstNMOS transistor having a drain connected to the output of the variabledelay circuit and a gate for receiving the clock signal; and a secondNMOS transistor having a drain connected to a source of the first NMOStransistor, a gate connected to an output of the second inverter and asource connected to a ground voltage.

According to another embodiment of the present invention, a pulsegenerator comprising a NOR gate for receiving a clock signal and anoutput of a variable delay circuit and outputting a first clock pulsesignal; a first inverter for receiving the output of the NOR gate andoutputs a second clock pulse signal; the variable delay circuit forreceiving the clock signal and an output of the first inverter, andfeeds the output signal back to the NAND gate; a second inverter forreceiving the output of the variable delay circuit; and a PMOStransistor having a drain for receiving the output of the variable delaycircuit, a source for receiving a power supply voltage, and a gate forreceiving an output of the second inverter.

According to another embodiment of the present invention, a pulsegenerator comprising a NOR gate for receiving a clock signal and anoutput of a variable delay circuit and outputs a first clock pulsesignal; a first inverter for receiving the output of the NOR gate andoutputting a second clock pulse signal; the variable delay for receivingthe clock signal and the output of the first inverter, and feeds theoutput signal back to the NAND gate; a second inverter for receiving theoutput of the variable delay circuit; a first PMOS transistor having adrain connected to the output of the variable delay circuit and a gatefor receiving the clock signal; and a second PMOS transistor having adrain connected to a source of the first PMOS transistor, a gateconnected to an output of the second inverter and a source connected toa power supply voltage.

According to another embodiment of the present invention, a pulsegenerator comprising a NOR gate for receiving a clock signal, an enablesignal and an output of a variable delay circuit and outputs a firstclock pulse signal; a first inverter for receiving the output of the NORgate and outputs a second clock pulse signal; the variable delay forreceiving the clock signal and an output of the first inverter, andfeeds the output signal back to the NAND gate; a second inverter forreceiving the output of the variable delay circuit; and a PMOStransistor having a drain connected to the output of the variable delaycircuit, a source connected to a power supply voltage, and a gateconnected to an output of the second inverter.

According to an eighth embodiment of the present invention, a pulsegenerator comprising a NOR gate for receiving a clock signal, an enablesignal and a output of a variable delay circuit and outputting a firstclock pulse signal; a first inverter for receiving the output of the NORgate and outputs a second clock pulse signal; the variable delay circuitfor receiving the clock signal and an output of the first inverter, andfeeds the output signal back to the NAND gate; a second inverter forreceiving the output of the variable delay circuit; a first PMOStransistor having a drain connected to the output of the variable delaycircuit and a gate for receiving the clock signal; and a second PMOStransistor having a drain connected to a source of the first PMOStransistor, a gate connected to an output of the second inverter, and asource connected to a power supply voltage.

According to exemplary pulse generator embodiments of the presentinvention, the number of gates constructing the flip-flop circuit may bereduced compared to a conventional pulse generator. Because there areless gates, power consumption and chip area of the circuit may bedecreased.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become readily apparent from the descriptionof the exemplary embodiments that follows, with reference to theattached drawings in which:

FIG. 1 illustrates a block diagram of a conventional pulse-basedflip-flop;

FIG. 2 illustrates a circuit diagram of a conventional pulse generator;

FIG. 3 a circuit diagram illustrating a pulse generator according to anexemplary embodiment of the present invention;

FIGS. 4, 5, 6, 7 and 8 are circuit diagrams illustrating an example of avariable delay circuits which may be used in the pulse generator of FIG.3;

FIGS. 9, 10, 11 and 12 are circuit diagrams illustrating example latcheswhich may be used in the pulse-based flip-flop of FIG. 1;

FIG. 13 is a circuit diagram illustrating a pulse generator according toanother exemplary embodiment of the present invention;

FIG. 14 a timing diagram illustrating an example of a pulse-basedflip-flop comprised of the pulse generator of FIG. 3 and the latch ofFIG. 9;

FIG. 15 is a circuit diagram illustrating a pulse generator according toanother exemplary embodiment of the present invention;

FIG. 16 is a circuit diagram illustrating a pulse generator according toanother exemplary embodiment of the present invention;

FIG. 17 is a circuit diagram illustrating a pulse generator according toanother exemplary embodiment of the present invention;

FIG. 18 is a circuit diagram illustrating a pulse generator according toanother exemplary embodiment of the present invention;

FIG. 19 is an operation timing diagram illustrating an example of apulse-based flip-flop including the pulse generator of FIG. 17 and thelatch of FIG. 9;

FIG. 20 is a circuit diagram illustrating a pulse generator according toanother exemplary embodiment of the present invention; and

FIG. 21 is a circuit diagram illustrating a pulse generator according toanother exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE INVENTION

Exemplary embodiments of the present invention are shown and described,with reference to the attached drawings. As will be realized, theinvention can be modified in various obvious respects, departing fromthe spirit and scope of the invention. Accordingly, the drawings anddescription are to be regarded as illustrative in nature, and notrestrictive.

FIG. 3 illustrates a circuit diagram of a pulse generator according toan exemplary embodiment of the present invention. The pulse generator300 may generate a first clock pulse signal and second clock pulsesignal ˜φ and φ in response to a clock signal CLOCK. The pulse generator300 may include a NAND gate 302 which may receive the clock signal CLOCKand an output of a variable delay circuit 306; a first inverter 304which may receive an output of the NAND gate 302; and the variable delay306 which may receive the clock signal CLOCK and an output of the firstinverter 304. The output of the NAND gate 302 may become the first clockpulse signal ˜φ and the output of the first inverter 304 may become thesecond clock pulse signal φ.

The pulse generator 300 may further include a second inverter 307 and anNMOS transistor 308. The second inverter 307 which may receive an outputof the variable delay circuit 306, and an output of the second inverter307. The output of the second inverter may be applied to a gate of theNMOS transistor 308. A drain of the NMOS transistor may be connected tothe output of the variable delay circuit 306, and a source of the NMOStransistor may be connected to a ground voltage VSS. The second inverter307 and the NMOS transistor 308 may prevent the output of the variabledelay 306 from floating when the logic level of the clock signal CLOCKmay be high.

The pulse generator 300 may be composed of three gates. Accordingly, thenumber of gates constructing the circuit may be reduced. Therefore, thepower consumption and/or chip area of the circuit may be decreased.

A variable delay 306 may be constructed in various ways. A variety ofexamples of the variable delay are illustrated in FIGS. 4, 5, 6, 7, and8. The variable delays 306 may include an input terminal P which mayreceive the clock signal CLOCK, an input terminal N for accepting anoutput of the inverter 304, and/or an output terminal OUT.

The variable delay 306 illustrated in FIG. 4 may include a PMOStransistor 402 and an NMOS transistor 404 both of which may be seriallyconnected between a power supply voltage VDD and a ground voltage VSS. Agate of the PMOS transistor 402 may serve as an input terminal P, a gateof the NMOS transistor 404 may correspond to an input terminal N, and adrain of the PMOS and a drain of the NMOS may be connected to an outputterminal OUT.

The variable delay 306 illustrated in FIG. 5 may include a PMOStransistor 502, a first NMOS transistor, and a second NMOS transistor504 and 506 both of which may be serially connected between a powersupply voltage VDb and a ground voltage VSS. A gate of the PMOStransistor 502 may serve as an input terminal P and a gate of the secondNMOS transistor 506 may be connected to an input terminal N. A drain ofthe PMOS transistor 502 and a drain of the first NMOS transistor 504 maybe connected to an output terminal OUT. The gate of the first NMOStransistor 504 may be coupled to a power supply voltage VDD.

The variable delay 306 illustrated in FIG. 6 may include a PMOStransistor 602 and an NMOS transistor 604 both of which may be seriallyconnected between a power supply voltage VDD and a ground voltage VSS. Adrain of the PMOS transistor 602 and a drain of the NMOS transistor maybe connected to an input of a first inverter 606. An output of the firstinverter 606 may be connected to an input of a second inverter 608. Agate of the PMOS transistor 602 may serve as an input terminal P, a gateof the NMOS transistor 604 may correspond to an input terminal N, and anoutput of the second inverter 608 may be connected to an output terminal

The variable delay 306 illustrated in FIG. 7 may include a firstinverter 702 and a second inverter 704 may be serially connected to aninput terminal N. A PMOS transistor 706 and an NMOS transistor 708 maybe connected between a power supply voltage VDD and a ground voltageVSS. A gate of the PMOS transistor 706 may serve as an input terminal Pand a drain of the PMOS transistor 706 and a drain of the NMOStransistor 708 may be connected to an output terminal OUT. A gate of theNMOS transistor 708 may be connected to an output of the second inverter704.

The variable delay 306 illustrated in FIG. 8 may include a PMOStransistor 802 and first and second NMOS transistors 804 and 806 both ofwhich may be serially connected between a power supply voltage VDD and aground voltage VSS. A gate of the PMOS transistor 802 may serve as aninput terminal P and gates of the first and second NMOS transistors 804and 806 may serve as inputs for a terminal N. A drain of the PMOStransistor 802 and a drain of the first NMOS transistor 804 may beconnected to an output terminal OUT.

FIGS. 9, 10, 11 and 12 illustrate various examples of a latch that maybe used in the pulse-based flip-flop 100 (for example, the oneillustrated in FIG. 1).

The latch 900 of FIG. 9 may include a first inverter 902, which mayreceive a data input signal DIN in response to a first clock pulsesignal and a second clock pulse signal ˜φ and φ, a second inverter 904,which may receive an output of the first inverter 902, a third inverter906, which may receive an output of the second inverter 904 in responseto the first and second clock pulse signals ˜φ and φ, and a fourthinverter 908, which may receive the output of the first inverter 902. Anoutput of the fourth inverter may be outputted as a data output signalDOUT. The output of the second inverter 904 may be connected to theoutput of the first inverter 902. The latch 900 may output the datainput signal DIN as the data output signal DOUT in response to a fallingedge of the first clock pulse ˜φ and a rising edge of the second clockpulse φ.

The latch 1000 shown in FIG. 10 may include a first AND gate 1002 forreceiving a data input signal DIN and an inverted scan enable signal˜SE, a second AND gate 1004, which may receive a scan input signal SIand a scan enable signal SE, a NOR gate 1006, which may receive anoutput of the first and second AND gates 1002 and 1004 in response to afirst clock pulse and a second clock pulse signal ˜φ and φ, firstinverter 1008 which my receive the output of the NOR gate 1006, a secondinverter 1010, which may receive an output of the first inverter 1008 inresponse to the first and second clock pulse signals ˜φ and φ, and athird inverter 1012 which may receive the output of the NOR gate 1006and may output a data output signal DOUT. An output of the secondinverter 1010 may be connected to the output of the NOR gate 1006.

The latch 1000, which may receive the scan input signal SI as its inputsignal when the scan enable signal SE, may be activated at a logic highlevel, and may receive the data input signal DIN as its input signalwhen the scan enable signal SE may be inactivated at a logic low level.Then, the latch may output the received input signal as a data outputsignal DOUT in response to the first clock pulse signal and the secondclock pulse signal ˜φ and φ.

The latch 1100 illustrated in FIG. 11 may include a first inverter 1102for receiving a data input signal DIN in response to a first clock pulsesignal and a second clock pulse signal ˜φ and φ, a NAND gate 1104, whichmay receive an output of the first inverter 1102 and a set signal ˜SETas its input signals, a second inverter 1106, which may receive anoutput of the NAND gate 1104 in response to the first and second clockpulse signals ˜φ and φ, and a third inverter 1108, which may receive theoutput of the first inverter 1102 and may output a data output signalDOUT. An output of the second inverter 1106 may be connected to theoutput of the first inverter 1102.

The latch 1100 may output the data input signal DIN as the data outputsignal DOUT in response to the first clock pulse signal and the secondclock pulse signal ˜φ and φ, when the set signal ˜SET may be inactivatedat a logic high level, and may set the data output signal DOUT to alogic high level when the set signal ˜SET may be activated at a logiclow level.

The latch 1200 illustrated in FIG. 12 may include a first inverter 1202which may receive a data input signal DIN in response to a first clockpulse signal and a second clock pulse signal ˜φ and φ, a NOR gate 1204,which may receive an output of the first inverter 1102 and a resetsignal RESET as its input signals, a second inverter 1206, which mayreceive an output signal of the NOR gate 1204 in response to the firstand second clock pulse signals ˜φ and φ, and a third inverter 1208,which may receive the output signal of the first inverter 1202 and mayoutput a data output signal DOUT. An output of the second inverter 1206may be connected t6 the output of the first inverter 1202.

The latch 1200 may output the data input signal DIN as a data outputsignal DOUT in response to the first clock pulse signal and the secondclock pulse signal ˜φ and φ, when the reset signal RESET may beinactivated at a logic low level, and may reset the data output signalDOUT to a logic low level when the reset signal RESET may be activatedat a logic high level.

FIG. 13 illustrates a circuit diagram of a pulse generator 1300according to another embodiment of the present invention. Referring toFIG. 13, the pulse generator 1300 may be distinguished from the pulsegenerator 300 of FIG. 3 in that it may further include a second NMOStransistor 1309, which may be connected between an output of a variabledelay circuit 1306 and a first NMOS transistor 1308, and gated to aclock signal CLOCK. The second NMOS transistor 1309 may be added to thepulse generator 300 of FIG. 3 in order to prevent a current path to aground voltage VSS from being formed until the NMOS transistor 308 maybe turned off for a period during which the output of the variable delaycircuit 1306 may be increased to a logic high level. That is, when theoutput of the variable delay circuit 1306 may be increased to a logichigh level in response to a logic low level of the clock signal CLOCK,the second NMOS transistor 1309 may be turned off to cut off a currentpath between the output of the variable delay 1.306 and the groundvoltage VSS.

FIG. 14 illustrates an operation timing diagram of the pulse basedflip-flop when a first clock pulse signal and a second clock pulsesignal ˜φ and φ, generated by the pulse generator 300 (illustrated inFIG. 1) according to an exemplary embodiment of the present inventionmay be applied to the latch 900 illustrated in FIG. 9. A data inputsignal DIN may be outputted as a data output signal DOUT in response tothe first clock pulse signal and second clock pulse signal ˜φ and φ bothof which may be generated according to a rising edge of the clock signalCLOCK. The operation timing diagram illustration in FIG. 14 may also beapplied to the operation of a pulse-based flip-flop comprised of thepulse generator 1300 of FIG. 13 according to another exemplaryembodiment of the present invention and the latch 900 of FIG. 9.

FIG. 15 illustrates a circuit diagram of a pulse generator 1500according to another exemplary embodiment of the present invention. Thepulse generator 1500 may be operated as the pulse generator 300 of FIG.3 when an enable signal ENABLE may be activated to a logic high level.The pulse generator 1500 may include a NAND gate 1502 which may receivea clock signal CLOCK, the enable signal ENABLE and an output signal of avariable delay circuit 1506, an inverter 1504, which may receive anoutput signal of the NAND gate 1502, and the variable delay circuit1506, which may receive the clock signal CLOCK through an input terminalP, and which may receive an output signal of the inverter 1504 throughan input terminal N. The output signal of the NAND gate 1502 may serveas a first clock pulse signal ˜φ and an output signal of the inverter1504 may serve as a second clock signal φ.

The pulse generator 1500 may further include a second inverter 1507,which may receive the output signal of the variable delay circuit 1506,and an NMOS transistor 1508 that may be connected between the output ofthe variable delay circuit 1506 and a ground voltage VSS, and gated tothe output of the second inverter 1507 in order to prevent the output ofthe variable delay circuit 1506 from floating during a logic high levelperiod of the clock signal CLOCK. It is apparent to those skill in theart that the variable delay circuit 1506 may be replaced with one of thecircuits illustrated in FIGS. 4, 5, 6, 7 and/or 8.

FIG. 16 illustrates a circuit diagram of a pulse generator 1600according to another exemplary embodiment of the present invention. Thepulse generator 1600 may operate as the pulse generator 1300 of FIG. 13when an enable signal ENABLE may be activated to a logic high level. Thepulse generator 1600 may include a NAND gate 1602, which may receive aclock signal CLOCK, the enable signal ENABLE and an output signal of avariable delay circuit 1606, a first inverter 1604, which may receive anoutput signal of the NAND gate 1602, and the variable delay circuit1606, which may receive a clock signal CLOCK through an input terminal Pand may receive an output signal of the first inverter 1604 through aninput terminal N. The output signal of the NAND gate 1602 may serve as afirst clock pulse signal ˜φ and the output signal of the inverter 1604may serve as a second clock pulse signal φ.

The pulse generator 1600 may further include a second inverter 1607,which may receive the output signal of the variable delay circuit 1606,and a first NMOS transistor and a second NMOS transistor 1608 and 1609both of which may be serially connected between the output of thevariable delay circuit 1606 and a ground voltage VSS. A gate of thefirst NMOS transistor 1608 may be connected to an output of the secondinverter 1607 and a gate of the second NMOS transistor 1609 may beconnected to the clock signal CLOCK.

FIG. 17 illustrates a circuit diagram of a pulse generator 1700according to another embodiment of the present invention. The pulsegenerator 1700 may include a NOR gate 1702, which may receive a clocksignal CLOCK and an output signal of a variable delay circuit 1706, aninverter 1704, which may receive an output signal of the NOR gate 1702,and the variable delay circuit 1706, which may receive the clock signalCLOCK and an output signal of the inverter 1704. The output signal ofthe NOR gate 1702 may serve as a first clock pulse signal ˜φ and theoutput signal of the inverter 1704 may serve as a second clock pulsesignal φ.

The pulse generator 1700 may further include a PMOS transistor 1708 anda second inverter 1707, which may receive the output signal of thevariable delay circuit 1706, a PMOS transistor 1708 that may beconnected between the output of the variable delay circuit 1706 and apower supply voltage VCC and gated to an output of the second inverter1707 in order to prevent the output of the variable delay circuit 1706from floating during a logic low level period of the clock signal CLOCK.

FIG. 18 illustrates a circuit diagram of a pulse generator 1800according to another exemplary embodiment of the present invention. Thepulse generator 1800 may be distinguished from the pulse generator 1700of FIG. 17 because it may further include a second NMOS transistor 1809,which may be connected between an output of a variable delay circuit1806 and a first PMOS transistor 1808, and gated to a clock signalCLOCK. A second PMOS transistor 1809 may be added to the pulse generator1700 of FIG. 17 in order to prevent a current path from a power supplyvoltage VCC from being formed until the PMOS transistor 1708, which maybe turned off for a period during which the output of the variable delaycircuit 1706 may be decreased to a logic low level. That is, when theoutput of the variable delay circuit 1806 may be decreased to a logiclow level in response to a logic high level of the clock signal CLOCK,the second PMOS transistor 1809 may be turned off to cut off a currentpath between the output of the variable delay circuit 1806 and the powersupply voltage VCC.

FIG. 19 illustrates an operation timing diagram of a pulse-basedflip-flop comprised of the pulse generator 1700 of FIG. 17 according toanother embodiment of the present invention and the latch 900 of FIG. 9.A data input signal DIN may be outputted as a data output signal DOUT inresponse to a first clock pulse signal and a second clock pulse signal˜φ and φ that may be generated according to a falling edge of a clocksignal CLOCK. The operation timing diagram illustrated in FIG. 19 mayalso be applied to the operation of a pulse-based flip-flop comprised ofthe pulse generator 1800 of FIG. 18 according to the exemplaryembodiment of the present invention and the latch 900 of FIG. 9.

FIG. 20 illustrates a circuit diagram of a pulse generator 2000according to another exemplary embodiment of the present invention. Thepulse generator 2000 may operate as the pulse generator 1700 of FIG. 17when an enable signal ENABLE may be activated to a logic low level. Thepulse generator 2000 may include a NOR gate 2002 which may receive aclock signal CLOCK, the enable signal ENABLE and an output signal of avariable delay circuit 2006, a first inverter 2004, Which may receive anoutput signal of the NOR gate 2002, and the variable delay circuit 2006which may receive the clock signal CLOCK through an input terminal P andwhich may receive an output signal of the first inverter 2004 through aninput terminal N. The output signal of the NOR gate 2002 may serve asthe a clock pulse signal ˜φ, and the output signal of the first inverter2004 may serve as a second clock pulse signal φ.

The pulse generator 2000 may further include a second inverter 2007,which may receive the output signal of the variable delay circuit 2006,and a PMOS transistor 2008 that may be connected between the output ofthe variable delay circuit 2006 and a power supply voltage VCC and gatedto the output of the second inverter 2007.

FIG. 21 illustrates a circuit diagram of a pulse generator 2100according to another exemplary embodiment of the present invention. Thepulse generator 2100 may operate as the pulse generator 1300 of FIG. 13when an enable signal ENABLE may be activated to a logic high level. Thepulse generator 2100 may include a NOR gate 2102 which may receive aclock signal CLOCK, the enable signal ENABLE and an output signal of avariable delay circuit 2106, a first inverter 2104 which may receive anoutput signal of the NOR gate 2102, and the variable delay circuit 2106which may receive the clock signal CLOCK through an input terminal P andfor receiving an output signal of the first inverter 2104 through aninput terminal N. The output signal of the NOR gate 2102 may serve as afirst clock pulse signal ˜φ, and the output signal of the first inverter2104 may serve as a second clock pulse signal, φ.

The pulse generator 2100 may further include a second inverter 2107which may receive an output signal of the variable delay circuit 2106and a first PMOS transistor and a second PMOS transistor 2108 and 2109that may be are serially connected between the output of the variabledelay circuit 2106 and a power supply voltage VCC. A gate of the firstPMOS transistor 2108 may be connected to an output of the secondinverter 2107 and a gate of the second PMOS transistor 2109 may beconnected to the clock signal CLOCK.

Although FIG. 14 illustrates the operation of a flip-flop comprised ofthe pulse generator of FIG. 3 and the latch of FIG. 9, and FIG. 19illustrates the operation of a flip-flop comprised of the pulsegenerator of FIG. 17 and the latch of FIG. 9, any combination of pulsegenerators and latches would be apparent to anyone skilled in the artbased on the teaching of the preset specifications to construct aflip-flop. In addition, PMOS transistors, NMOS transistors, high and lowsignals, and logic gates may be substituted with equivalent transistors,low and high signal, and logic gates as would be known to one skilled inthe art.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims.

1-68. (canceled)
 69. A variable delay comprising: a PMOS transistorhaving a gate connected to an input signal and a drain connected to apower supply; and a first NMOS transistor having a drain connected tothe source of the PMOS transistor; and a final output that is a delay ofthe input signal.
 70. (canceled)
 71. (canceled)
 72. A pulse generatorincluding the variable delay of claim
 69. 73. A flip-flop including thepulse generator of claim 72.